FPGA and Digital Systems
Completed
Digital design coursework focused on FPGA development, Verilog-based hardware design, simulation, and hardware validation using programmable logic systems.
My work: implemented combinational and sequential Verilog modules, multiplexers, latches, flip-flops, counters, ALU-style logic, state machines, Booth/bit-pair recoded multipliers, and modular processor-style datapaths. Developed behavioral, gate-level, and dataflow models alongside simulation testbenches for validating timing behavior, edge cases, clocked logic, and sequential state transitions. Completed board-level FPGA exercises involving hardware I/O mapping, timing constraints, debugging, and synthesis validation.
Hardware / software: Pynq-Z2 FPGA board, Verilog HDL, Vivado, Vitis, XDC constraints, waveform simulation, behavioral simulation, synthesis/implementation flows, finite state machines, pipelining concepts, hardware timing analysis, and FPGA hardware debugging.